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09-09-2013 06:39 AM

Current Mode Control

Many years ago (too many!) I took on the problem of current-mode control modeling. In 1986, there were at least 6 different schools of thought on how current mode control should be modeled. Then, within those 6, there were three major ways of trying to analyze the system using approximate average models.

Dr. Fred Lee's model at Virginia Tech used one approach, and NASA publications followed this approach. Then, Middlebrook at Caltech came out with another way to look at the problem and of course, being Middlebrook, it was highly respected. Vince Bello, someone who did a lot of Spice modeling for the industry had another approach.

All three approaches had a different way of analyzing the gain of the current-mode modulator, and they all came out with different results. Very different.

All of these were smart people, and their mathematical derivations looked good. Who is going to find a mistake in Middlebrook's work?

I avoided the problem of trying to figure out where the mistakes might be by making measurements on the system to see who had it right. And, only one of them was right, not including Middlebrook or Lee, my advisor.

In the interests of discretion, I didn't pursue the issue further, I just went with reality from the measurement, so no one had to dwell on people making errors of any kind. I really thought that hardware confirmation of what was correct would be sufficient, and the topic would be closed.
Unfortunately not, and publications on current mode continued for many years, from high-ranking researchers who continued to get it wrong. A recent publication even tried to reconcile the differences into one model, making it look like they all had it right.

Finally, three years ago, I decided to go and revisit the topic again, and I found out where the fundamental assumptions led to errors. I have never published it, although I did present it one time at APEC. (I'll be presenting it again in Nuremberg next month.)

My plan is to put it into a book on current mode, set the record straight, and maybe kill off the topic once and for all. At the same time, I will update my dissertation, print it in color, and make it very accessible, I hope.

So the question is this: does anyone out there really care to have this history? Would it be a worthwhile endeavour?
09-09-2013 06:39 AM
Top #2
09-09-2013 06:39 AM
YES! I am very interested in a lot of the historical development of power electronics. (See my various questions about the PWM models in one of the other discussion). In particular, I'm interested in the development of converter modeling - SSA, switching models and (why) all the variants, etc. and current mode control. I enjoy any tidbits on the various personalities involved and the various debates that went on back in the day (and still today, I'm sure). I have also on occasion for fun tried to see how far back in the literature I can go. For example, going to Gene Wester's dissertation and then looking at his references and so on.. I would still like to know where the first basic inductor charge balance analysis was done on basic buck, boost, and buck/boost..
09-09-2013 06:40 AM
Top #3
09-09-2013 06:40 AM
I have found the trail of papers from the seventies a very interesting part of electronics history, culminating in your paper explaining the inner current loop to operate as a sample data system with inherent double poles at the half sample (switch) frequency.

I trim my current mode loop by simulation in SIMPLIS with all relevant parasitics as I can quantify the degree of slope compensation as a gain margin at fsw/2. My customer understands Gain and Phase margins but not neccessarily current mode operation and slope compensation.

Keep it simple and you will have a wide audience.
09-09-2013 06:40 AM
Top #4
09-09-2013 06:40 AM
The history could be very interesting to note the path various "experts" took.
Like all progress, one must stand on the shoulders of others before.
If you can, show how the erroneous assumptions were made and how the "measured" data dispels the assumptions. This may infer new review of other academia exposures and discover other mis-assumptions.
So much taught in school are generalizations... hence E=mc² ± 3dB is more accurate than most would believe.
09-09-2013 06:41 AM
Top #5
09-09-2013 06:41 AM
Absolutely, since I still like to put pencil to paper as opposed to strictly using computer simulation...I'd love to be able to accurately derive the analytical model for current-mode control for many of the power supplies I design.
09-09-2013 06:41 AM
Top #6
09-09-2013 06:41 AM
Wow, I am overwhelmed by the response. I am glad that so many people are interested. It is a big hole in the body of work which no one has seemed to question except me so far.

Regarding the comment from Garry DuBose, the PSpice model listing is available at our website. If you download the current-mode dissertation, the last chapter has the complete listing ready to put into PSpice.

POWER 4-5-6, for those of you that have it, automatically fills in all of the model values for you.

When I get to publish it, I think you will find it interesting. Only one modulator gain is right, but no one made an apparent mistake. At the same time, they all made the same error.

If you come to Nuremberg, you'll get a preview in the Sunday seminar. As I mentioned before, I presented this once at APEC, but I'm not sure anyone really got what I was saying at the time.
09-09-2013 06:42 AM
Top #7
09-09-2013 06:42 AM
Proving people wrong is not a bad thing. In fact, clarity is much needed. As a PhD student studying converters and topologies I have been learning a lot about the background and (as people mentioned before) trying to stand on the shoulders of giants is what we aspire to do but if those shoulders are not as broad or high as one assumes then the result is of less use.

I recently ran into an issue with setting up converters in series that I could not explain until I drew the inductor currents versus the duty cycle time to realise what the problems are there. Yet, while there maybe papers about a lot of people discussing topologies do not include these finds in their papers which I think is a big miss in the distribution of knowledge.

So, yes, publish. rather sooner than later and I would be very interested to read about. You mentioned you discussed this earlier is there a paper of this out already? And if so, could you mention it here so I can find it?
09-09-2013 06:42 AM
Top #8
09-09-2013 06:42 AM
The Li dissertation is on my list of things to cover.

For some reason he worked hard on proving that my model was inadequate. There was quite a bit of focus on the constant on-time controller, and you will find a plot of my model vs a Simplis plot. He claimed that my model was "fixed" with an arbitrary phase lead. When plotted without the phase lead, the agreement was poor. Well, if you throw out a part of the model, of course it will not be good!

I remember well finding in the lab the phase lead issue. I went back to some early Middlebrook papers on modulators, and found that, indeed, the constant on-time modulator has a phase lead which is dependent on duty cycle. It was a strange thing to find - you normally expect modulators to have a phase delay, not lead!

I confirmed it in the lab by measurement with an HP4194, and that is in my dissertation. However, that was dismissed by Li with the statement "In order to correct the error, an additonal term Fc, which has a phase-leading characteristic, must be added based on experiment data, which is lacking of theoretical analysis, as shown in Figure 1.29 and Figure 1.30. " I wish people would pick up the phone and call past authors before putting these things into print. There was plenty of theoretical basis for the phase lead, it is well known by those who have investigated it.

There was one more slight discrepancy on audiosusceptibiliy at higher frequencies, but that really is insignificant. And Li took the step of comparing theory with simulation, rather than making measurements. I don't really like that approach, you always wonder whether the simulator is doing things right, but it's not really important.

The big deal, to me, about the Li dissertation was that he rediscovered Vorperian's model after much mathematical contortion. In terms of the model he arrived at, I don't really see any contribution beyond what Vorperian had already done. Also, the circuit model is missing the input components that Vorperian came up with, I'm not sure I understand that, or why the reference wasn't made to Vorperian when the circuit model with the cap on the output of the switch cell was arrived at. Maybe I overlooked the reference.

There is discussion of Tan's model, and how mine is "more popular". It could be that is because the Tan model in not verified when the current loop is measured. To me that is a serious issue if the inner loop measures wrong, even if you eventually end up with the right outer transfer function.

The digital part of the dissertation is probably useful. I'd be interested in other comments.

More than I meant to write - sorry about that. (Please, don't anyone bring up the Verghese paper from MIT!)
09-09-2013 06:43 AM
Top #9
09-09-2013 06:43 AM
If a SMPS has proper slope compensation for peak current mode control (PCMC), the effect of the current gain, output inductor and switching all combined, gives a simple current source stage and a zero-order hold. You can estimate the effective phase shift of the ZOH by: Phase = 180*(F/Fsw). and the current gain stage is simply: 1/(Rcs).

If your gain rolls off at 1/10th the switching frequency for example, the effective phase shift will be 18deg (additional to your ideal bode plot of a non-sampling system). You can verify this by making a simple spice model of a few R+C+ gain stages followed by a sample hold. You'll see that your little model starts to oscillate when you raise the gain above zero at the point where your bode (including that sampling phase shift) crosses 180.
I worked with Ridley's CMC model with slope-comp a few years ago and found too, that this model accurately predicts the phase shift due to sampling (as well as showing the common 'subharmonic distortion if the amount of slope-comp is not enough).
The paper on slope compensation and PCMC from Barney Holland 30 years ago explained in a very clear manner how and why slope-comp works. Using the simple phase shift model I stated or using an elegant switching model like the one Ray developed, we should be "there" and current mode control shouldn't have to be looked at as mysterious anymore.
09-09-2013 06:43 AM
Top #10
09-09-2013 06:43 AM
I agree, it shouldn't be mysterious any more. I believe the last substantive contribution to current-mode was Vorperian's paper on the current mode switch in 1991.

Trouble is, many subsequent papers muddied the waters again so newcomers to the field can easily be confused.

Barney Holland really had it all solved nicely in that paper long ago, but didn't apply any math to the technique.
09-09-2013 06:44 AM
Top #11
09-09-2013 06:44 AM
I have always maintained that the effective sampling process block, HSP, should be inserted in the forward path just prior to the power stage (beyond the point where all feedback paths have joined together). This correctly locates HSP such that the PWM process delay will equally affect any type of feedback, including “pure” voltage mode control. In most cases, voltage mode control implicitly includes some amount of high frequency current feedback (and load current feedforward, as well) either through the mechanism of output capacitor ESR or an explicit high frequency zero (phase lead network) in the feedback path.

In order to model current mode instability (subharmonic oscillations at 50% duty cycle and ½ fsw), current loop gain must be unity and current loop phase must be -360° (the well-known Nyquist-Barkhausen criterion). Since inductor current phase is -90° (low frequency pole) and the current comparator negative feedback adds an additional -180°, the sampling process, HSP (s), phase lag must be -90° (at ½ fsw). Therefore, in order to achieve unity gain at ½ fsw, the sampling process gain factor must be π/4.

What linear network can approximate HSP (the sampling process) at dc and ½ fsw? Many networks can fulfill this requirement, but the simplest is an LRC low pass. A current fed CLR pi-network is perhaps computationally “friendliest” for simulation, which is my interest.

Use C= 4/(pi^2*fsw), L= 1/(4*fsw) and R=1 (then Q= pi/4.

Note that at resonance, gain = Q and phase = -90°, which greatly simplifies the calculation of component values.
09-09-2013 06:44 AM
Top #12
09-09-2013 06:44 AM
There is a linear circuit model to do what you say in the appendix of my dissertation in the design center. A simple spice model with L and C, probably the same value as yours.
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