These are now ubiquitous all over the industry. Invented decades ago, but finally becoming essential with ever-lowering output voltages.

What are the secrets to successful drives and timing to maximize efficiency?

I see lots of new engineers trying to implement them without the background needed and without the experience, thinking it will be a simple task.

What is your advice and experience?

As a general rule, at what output voltage do you consider them to be an essential part of modern technology?

What should newcomers to the technology beware of?

I first started investigating synchronous rectifiers over 20 years ago. I had actually wrote product proposals for a MOSET with a schottky diode in parallel with the MOSFET's antiparallel diode. I nicknamed it the FETSKY, but it was deemed to ethnic. IR beat me to the patent office calling theirs the FETKY. I had developed, with a Si designer, the integrated FETSKY ISchottky on same die as the MOSFET). Now Fairchild has the SYNCFET.
For hard switching circuits, I had found that adding a sync rect above 5V output only added, at most, 1.5% in efficiency. The higher the output V, the less improvement. Here, it is a matter of BOM cost verses the improvement in efficiency.
Below 5V, especially less than 2.5V, It is mandatory with improvements of over 10%, if done right. Deadtime timing is critical. Also the use of an antiparallel schottky diode is very important. The schottky provides a lower reverse voltage without a reverse recovery effect. The schottky only works foe a small period because its resistive forward voltage characteristics increases until the P-N diode begins to conduct. Then the P-N reverse recovery comes into play, thus removing all of the schottky's benefit.
A deadtime of 35 to 90 nS seems optimum.

The statements Marty makes would be mine also except for the deadtime. I have used synchronous rectifiers since the late 80's, even at high voltages (400 to 200V converters). I would say deadtimes should be based on layout, topology (LLC is different than high voltage which is different from low voltage) packaging and switch technology; there is no single optimum point for all applications. Indeed some of the high side drive IC's will limit your ability to get deadtimes much below 250nS simply due to prop delay but some manufacturers suggest 500nS as minimum. Capacitive displacement currents (causing heat in the device) in the drive ICs limit the upper frequency in high voltage designs.Boost phenomena during transients can be a problem in higher voltage converters. The lower switch keeps turning on to lower the Vout and kicks energy back through the upper body diode to form a boost converter that can pump up the bulk supply (this can make a mess of the PFC function in high voltage applications).Newer technologies in switches (MOSFETs) allow for optimal drive voltages to be in the 1.8 to 2.2 V volt regions (for low voltage designs) on the gates although the Miller glitch on the lowside gate becomes more problematic. In these designs packaging is everything, then layout is more. In these systems you can have very short deadtimes (but I can't say how short; NDA don't you know).Invented decades ago? No, as I posted before, 1834 was when it showed up.

I think these days the voltage is going high and the efficiency gains climbing because of the better quality parts. I see they sync rectifiers at surprisingly high voltages. Perhaps someone can comment on the highest voltage they have seen them used and the efficiency gains observed.

Pardon my confusion but ... are we talking "secondary" synchronous rectifiers or the non isolated synchronous buck ??

Doesn't really matter - if a switch is being used in place of a diode, it's a synchronous rectifier.

They are even appearing in the bridgeless PFC circuits nowr on the input of the power supply.

Dr. Ridley,

Oops! I wrote my last email a few minutes after your response re the definition of a synchronous rectifier. I hadn't seen it yet.

You've answered my (first) question. Thanks.

R. Steve Scott

Hello chaps, just an observation. Beware of the MOSFETs dissipation when the system start's up and shuts down - a higher Vgs and a low tx impedance can mean lots of power through the MOSFETs if only for a small period. Dependent on architecture and control; some setups use the voltage from the secondary to drive the MOSFETs. Also that goes for the threshold voltage of the MOSFETs and the variation in that voltage from part to part - a narrow Vgs band is more suitable.
I have seen in audio applications that this kind of rectifier is more suitable because of the diode recovery time and in turn voltage spikes (which should be minimal) - the secondary voltages for these applications can be from 12V to 80V.

Ray and Sanjay,

I hear my previous email got erased by mistake. I'll try to remember at least part of what it said...

I had intended to ask Dr. Ridley the same question as Sanjay regarding whether he was thinking about synchronous rectifiers (SRs) directly connected to the output or those on the secondary side of a transformer, or "all of the above". But he answered this question just as I was commenting!

I also opined that this could be a very useful discussion. I personally have very little knowledge about SRs. I think both Marty and Ron's comments were very instructional. I'd like to hear even more about deadtime recommendations, the useful voltage range for SRs, etc.

I think I also asked if anyone had ever successfully designed a sync rectifier WITHOUT using a FET(S)KY type switch (I'm aware of the MOS body diode reverse recovery issue, but I wonder if anybody has found synchronous rectification useful even with no Schottky?)

I think I also asked for recommendations for appropriate gate driver ICs (for direct and secondary-side SR's) and for any recommendations on how to time/drive secondary side SRs (and if switch timing needs to be transferred from primary to secondary side via a separate isolator, and how this is best achieved).

R. Steve Scott

Marty:

You seem to have considerable experience. And you've found that:

"A deadtime of 35 to 90 nS seems optimum"

But the optimum deadtime depends on manufacturing tolerances, temperature, supply voltage, load impedance etc.

So should we use the tried-and-true engineering principles of "worst case corners" "better safe than sorry" etc.. and set the deadtime for more than 90 nS?

Or design an inner control loop to optimize the deadtime in any situation?