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08-29-2013 09:48 PM

Synchronous Rectification and Power Mosfets

Hi folks, I'm reviewing a design about a power converter for driving an electromagnet (10A, 50V).

The substitution of a freeweeling diode with a N-channel enanchement mosfet it's a good choice for reducing dissipated power which is relevant on the diode.

I'm just wondering about the current direction in the N power mosfet: from Source to Drain in this arrangement. The flow is opposite respect to the "normal" one.

Ok, nothing strange in a planar mosfet which is geometrically simmetric (source and drain may be reversed if you want - ignoring that the sub is connected to the source) but what about a vertical power mos ?

When current flows from drain to source with Vgs > VT (enanchement N mos) the channel acts as a "low" value resitor if Vds remains far from the pinch-off condition Vgs-Vds >> VT.
Voltage channel drop from drain to source affect this condition.

How about the pinch off condition where the current flow in the opposite direction and the geometry of the VMOS is asimmetric?

I'm just curious about that.

Thanks !
08-29-2013 09:49 PM
Top #2
08-29-2013 09:49 PM
Hi Enzo,

Yes-- the current flow is opposite what you usually encounter: it goes source-to-drain. You bring up an interesting question-- about the geometries of the trench-FET-- they are not symmetrical like how planars are typically depicted.

Trench FETs are frequently used as a synchronous rectifier in place of a free-wheeling diode in buck/forward and also in the outputs of flyback converters.

These devices are typically run deep into saturation to avoid any pinch-off problems. Most vertical structure MOSFET devices exhibit a secondary breakdown-- hot-spotting effects that run away in a manner that planar FETs do not tend to do. Staying within the safe-operating area if you spend any length of time in the FET's linear region can be difficult. I just had a series of customers with failures due to SOA excursions.

A modern 100V trench MOSFET can have an R_ds:on < 7mOhm-- so the V_ds (or V_sd, in this mode) remains very small. Pinch-off in switch-mode power supplies with these devices is rarely a problem.

Some applications take advantage of the body diode to conduct for small amounts of time on the leading/trailing edge of the switching waveform. At immediate turn-off of the high-side MOSFET, the low-side MOSFET body diode will conduct, followed very shortly by low-side gate drive to enhance the low-side MOSFET (making the device behave more like an ideal diode). Very shortly before the high-side MOSFET is turned on, the low-side gate will be brought low (forcing current through body diode)-- but this helps prevent shoot-through (current passing straight from the circuit power source through high-side MOSFET through low-side MOSFET to ground). Fairchild offers FETs with Schottky diodes in parallel to handle the current from the body diode-- it offers better switching characteristics. Some of the other Semi's offer this as well.
09-02-2013 10:10 PM
Top #3
09-02-2013 10:10 PM
Dear Daniel,
thank you very much for your detailed explanation!

Please, let me summarize just for verifying If I understood correctly.
Early power mosfets (e.g. Vmos, Siliconix 1976) were conceived as asymmetric for exploiting "large" drain areas. This allowed to better dissipate power generated close to the drain electrode because of the pinch-off phenomenon.
Such an architecture could work both in active region (saturation: drain at pinch-off) or in linear (low ohmic switch) region as well.
The passage from one region to the other (keeping Vgs constant) depends on the Vds drop along the channel.

Modern trench architectures for power mosfets (the ones you shown me), are again characterized by an asymmetrical structure in which drain takes a large silicon area.
By looking at the linked document from Fairchild, the function of such a large area is merely due to the need of paralleling several mosfets instead of allowing good power dissipation in the drain region.
In trench architectures the goal is to keep Rds as low as possible (reducing ohmic losses in the channel).
Because of this "extremely" low value of resistance, pinch-off condition is "not practically reachable" in this devices and their behavior looks "symmetric" (in the sense that you may have current flowing in both senses - from drain to source and vice versa) even if the geometry is not.

Definitely trench architectures are primarily conceived for function as switches instead of amplifiers. Maybe we can say that they "never" reach the pinch-off in a typical application.
what I understood is that in the medium voltage range (up to 100-200V), power trench mosfets with shielded gate technology exhibit extremely low Rds while maintaining superior switching performances (thanks to low values of parasitic capacitors present in the component).
For example in a half bridge arrangement (my case), I can use the same device for both hi-side switch (draining power from the supply) and for the low-side switch (re-circulating current trough the load with drain current goes in the opposite direction respect to "normal one" - i.e. from source to drain).

just the last questions:
Ok, modern trench architectures (e.g. shielded gate) are the best in class regarding switching time and power losses but what about the drawbacks respect to other power mosfet architectures?
maybe their are suitable only for low voltage application(?) - less than 200V.
09-02-2013 10:10 PM
Top #4
09-02-2013 10:10 PM
The biggest drawback of using MOSFETs for synchronous rectifiers is that to avoid shoot through, deadtime has o be added. During deadtime, current will flow through the body diode with charge stored in the PN junction. For an 8 mohm (25 C, max) MOSFET, this is specified as 62 nC. There are two problems with this:

At 200 kHz, 75 V, if 62 nC were indeed the actual stored charge, 0.93 W would be dissipated in reverse recovery.

Reverse recovery is poorly specified. the 62 nC cited is at 100 A/us and 25 C. I suggest that you ask the MOSFET vendor for reverse recovery charge at elevated temperature and realistic di/dt.

100 V, 7 mohm (25 C, max) enhancement mode gallium nitride on silicon FETs are available with zero reverse recovery charge. Using GaN on silicon keeps the cost of these competitive with silicon MOSFETs.
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